Conventional CMOS phase-frequency detector and charge-pump filter combinations used in synthesizers suffer from cross-over distortion in the region of zero phase difference between the input signals. This is primarily due to the asymmetrical configuration at the device level and the low speed of conventional CMOS gates 10 and switches, and it is commonly referred to as the dead-zone problem. High-speed synthesizers are much more susceptible to dead-zone distortion, because such distortion occurs for a larger portion of the cycle time.
In an attempt to overcome this problem, low-jitter synthesizer applications in the prior art employ fast devices such as bipolar NPNs, and utilize symmetric implementation of gates in fast logic families such as ECL (emitter coupled logic). All-NPN phase-frequency detectors and charge pumps, therefore, have been the preferred means for improving speed and reducing dead-zone-induced phase jitter.
If a state-of-the-art BiCMOS technology is not available, however, dead-zone effects and jitter become major concerns in CMOS-only synthesizer designs. It is the purpose of this invention to reduce jitter and improve synthesizer speed without the need for any technology other than CMOS.